Designing for Performance for CPLDs

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Designing for Performance for CPLDs is an intermediate-level course that provides a comprehensive overview of the CPLD software flow. By applying the techniques presented in this course, you will be able to enhance design performance and make the best possible use of Xilinx CPLD architectures.

This course uses the ISE™ 9.1 software, including the Constraints Editor and Timing Analyzer. Other topics include understanding the CPLD logic engine, estimating power, and fitting difficult designs.

After completing this comprehensive training, you will have the necessary skills to:

• Apply techniques to fit more logic into a device
• Describe the CoolRunner™-II CPLD timing model and how it can be used to analyze design performance
• Describe the advanced capabilities of the CoolRunner-II CPLD architecture
• Estimate the power consumption of a CPLD design