This is a flag ship course for designers who have a design under their belt and want to learn more in regards to improving performance and utilisation and how to debug their design. Everyone gets something from this course, even the most experienced.
Our first two days are spent looking deeper into the architecture to improve performance and utilisation. Just how is your code implemented in side an FPGA and what determines its performance.
Thje next 2 days are spent gaining a more advanced understanding of Vivado. Understand the underlying Vivado database, utilize Tcl for navigating the design, create Xilinx design constraints (XDC), and timing reports. Learn to make appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces for your FPGA design.
You will also learn to make path-specific, false path, and min/max timing constraints, as well as learn about timing constraint priority in the Vivado timing engine. Finally, you will learn about the scripting environment of the Vivado Design Suite and how to use the project-based and non-project batch flows.
The final day is dedicated to hands on practical debugging with the Vivado Logic Analyser
The Academy II
course consists of 3 packaged courses including:
Design Tips & Techniques for Low Cost (2 days)
Vivado Advanced XDC and STA for ISE Users (2 days)
Debugging Using the Vivado Logic Analyzer ( 1 day)