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2011 Full Course Schedule Dates
Online Training
Xilinx Academy Courses
FPGA Design Courses
»
 Designing with the 7 Series Family
»
 Xilinx FPGA Power Estimation
»
 ISE Design Tool Flow
»
 Essentials of FPGA Design
»
 FPGA Design Tips and Techniques
»
 Designing for Performance
»
 Advanced FPGA Implementation
»
 PlanAhead Advanced Design Techniques
»
 Debugging Techniques Using the ChipScope Pro Tools
»
 Designing with the Virtex-6
»
 Designing with the Spartan-6
»
 Designing with the Virtex-6 and Spartan-6
»
 PlanAhead Essentials
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PlanAhead Essentials

Learn to manage design performance, plan an I/O pin layout, and implement by using the PlanAhead™ software tool.  Topics include: a tool overview, running a Design Rule Check (DRC) and Simultaneous Switching Noise (SSN) analysis of pin assignments, design and timing analysis, creating cores, and completing synthesis and implementation with the PlanAhead tool.

After completing this comprehensive training, you will have the necessary skills to:
  • Use the PlanAhead tool features and benefits
  • Import designs into the PlanAhead tool project environment
  • Assign I/O pins and clock logic
  • Run DRC and SSN noise analysis
  • Integrate IP with the PlanAhead tool
  • Import HDL sources, elaborate, and analyze the RTL netlist
  • Implement the design with different implementation strategies
  • Analyze design statistics and timing
  • Use the PlanAhead tool integrated with the ISE tool Project Navigator environment  

 

 
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