Learn to increase design performance and achieve repeatable performance by using the PlanAhead™ software tool. Topics include: synthesis and project tips, design analysis, creating a floorplan, improving performance with area constraints and Pblocks, design debugging with the ChipScope™ Pro tool, and design preservation with partitions.
After completing this comprehensive training, you will have the necessary skills to:
Use the most advanced features of the PlanAhead tool
Apply the hierarchical viewer and timing report information to make the best area constraints
Group the best logic into Pblocks
Import HDL sources, elaborate, and analyze an RTL netlist
Implement the design with different implementation strategies
Analyze design statistics, connectivity, timing, placement, and timing critical paths
Insert ChipScope Pro tool debug cores
Floorplan the design to improve performance and preserve successful implementation results
Make placement constraints for dedicated hardware resources
This course is part of the Xilinx FPGA Academy III training course. You may attend the course seperately.