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Please click on the PDF below for a full course summary
This course appeals to engineers who have an interest in good design techniques, to produce compact design (for lower cost) with additional discussion on Logic Levels for Timing. The course and exercises cover several different design techniques, which will be interesting and challenging for any digital designer regardless of the final application.
After completing this comprehensive training, you will have the necessary skills to:
- Describe the Fabric features of the Spartan-3E and Virtex-5 devices
- Accurately estimate design size to aid in predicting product costs
- Apply design techniques that result in low-cost implementations
- Explore creative ways to use the FPGA memory resources to reduce design costs
We recommend this course with the Designing For Performance course as part of the Xilinx Academy II
Please confirm course schedule dates before purchase as courses will not run until minimum numbers are achieved. Courses
can be scheduled as required at short notice, often for very small
numbers so please call to have a course set up for you.
This course is part of the Xilinx FPGA Academy II training course. You may attend the course seperately.
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