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Designing with the UltraScale Architecture

          Take advantage of the primary UltraScale architecture resources

          Describe the new CLB capabilities and the impact that they make on your HDL coding style

          Define the block RAM, FIFO, and DSP resources available

          Properly design for the I/O and SERDES resources

          Identify the MMCM, PLL, and clock routing resources included

          Identify the hard IP resources available for implementing high-performance DDR4 memory interfaces

          Describe the additional features of the dedicated transceivers

          Effectively migrate your IP and design to the UltraScale architecture as quickly as possible

 

          Lab 1: Optimal Coding Styles for CLB Resources – Analyze a design that has asynchronous resets by generating various reports such as the Timing Summary report and Utilization report. Convert the asynchronous resets to synchronous resets by removing the reset signal from the sensitivity list. Also examine the CLB resources, such as the LUT and the dedicated carry chain.

          Lab 2: Clocking Migration –  Migrate a 7 series design to the UltraScale architecture with a focus on clocking resources.

          Lab 3: Clocking Resources –Use the Clocking Wizard to configure a clocking subsystem to provide various clock outputs and distribute them on the dedicated global clock networks.

          Lab 4: DDR3 MIG Design Migration – Migrate a 7 series MIG design to the UltraScale architecture. The provided MIG design was targeted to a Kintex® UltraScale device (KC705 evaluation board) with DDR3 memory on board. In this case, the design will be migrated to use an UltraScale DDR3 memory interface.

          Lab 5: DDR4 MIG Design Creation – Create a DDR4 memory controller with the Memory Interface Generator (MIG) utility.

          Lab 6: Component Mode I/O– Implement a high-performance, source-synchronous interface using the UltraScale architecture SelectIO in Component mode.

          Lab 7: QSGMII Design Migration – Migrate an existing 7 series QSGMII example design to a Kintex UltraScale architecture-based device. This lab will show you how to update your port connections and use the optimum logic resources available.

          Lab 8: 10G PCS/PMA and MAC Design Migration – Migrate a successfully implemented 7 series design containing 10G Ethernet MAC and 10G PCS/PMA IP to an UltraScale FPGA.

          Lab 9: Transceiver Core Resources – Use the Transceiver Wizard to build a design that uses a single serial transceiver and observe the file structures created.

 

 

 
Classroom  -  $1,250.00
   
   
 
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