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After completing this comprehensive training, you will
have the necessary skills to:
- Describe
all the functionality of the 6-input LUT and the CLB construction of the 7
series FPGAs
- Specify
the CLB resources and the available slice configurations for the 7 series FPGAs
- Define
the block RAM, FIFO, and DSP resources available for the 7 series FPGAs
- Properly
design for the I/O block and SERDES resources
- Identify
the MMCM, PLL, and clock routing resources included with these families
- Identify
the hard resources available for implementing high performance DDR3 physical
layer interfaces
- Describe the additional dedicated hardware for all the 7 series family
members
- Properly code your HDL to get the most out of the 7 series FPGAs
More details can be found in the course summary PDF below |