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Fundamentals of CPLD Design
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Designing for Performance for CPLDs

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Fundamentals of CPLD Design

Please click on the PDF below for a full course summary  

This comprehensive course provides you with an introduction to designing with Xilinx CPLDs by using the ISE™ series software tools. You will learn the basics of ISE software flow and how to interpret CPLD reports for optimum performance designs.

This course covers ISE features such as the Constraints Editor and PACE. Other topics include design planning, implementation options, and global timing constraints. You will ultimately configure a CPLD demo board by using Xilinx configuration software.

After completing this comprehensive training, you will have the necessary skills to:

  • Describe what products Xilinx offers and where the CoolRunner-II CPLD fits into this offering
  • Identify the basic architectural resources of the CoolRunner-II CPLD
  • Describe the CPLD tool flow: Design entry, synthesis, implementation, and programming
  • Specify global timing constraints and pin assignments
  • Access and implement basic and advanced CPLD software options via the ISE software 

Please confirm course schedule dates before purchase as courses will not run until minimum numbers are achieved. Courses can be scheduled as required at short notice, often for very small numbers so please call to have a course set up for you.

 
Live Instructor Led Online  -  $550.00
Both CPLD Courses Online  -  $900.00
   
   
 
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