Please click on the PDF below for a full course summary
Learn how to employ RocketIO™ GTP and GTX serial transceivers in your Virtex®-5 LXT, SXT, FXT, or TXT FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as CRC, 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture
Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.
After completing this comprehensive training, you will have the necessary skills to:
- Describe and utilize the ports and attributes of the RocketIO multigigabit transceiver in the Virtex-5 FPGA
- Effectively utilize the following features of the GTP/GTX:
- 8B/10B and other encoding/decoding, comma detection,
- CRC, clock correction, and channel bonding
- Pre-emphasis and linear equalization
- Use the GTP/GTX Transceiver Wizard to instantiate GTP and GTX primitives in a design
- Access appropriate reference material for board design issues involving the power supply, oscillators, and trace design
Please confirm course schedule dates before purchase as courses will not run until minimum numbers are achieved. Courses
can be scheduled as required at short notice, often for very small
numbers so please call to have a course set up for you.