To give you a clear learning flow and structure we have introduced our Academy Flow.
We discount the Academies compared to sitting on individual courses.
Courses can be attended Publically, Live Instructor Led online and Onsite for 4 or more people.
If you choose live instructor led online, then we can also schedule training to be paced over a number of weeks with 2-3 hr slots in the days or/and evenings.

 Academy I introduces you to the ISE design flow, gives you 3 days comprehensive training on VHDL, and finishes off with a day understanding the basics of the FPGA, Timing, and the implementation flow.

 Academy II gets you more involved with design tips, techniques, timing constraints, and timing closure.

 Academy III is much more involved with UCF, IO Contraints for SDR DDR Source and System synchronous design, PlanAhead for Timing closure, run times and utilisation, Chipscope, adding Probes, Partitions, Guided implementation, TCL scripts and more!

 Please consider the Academy II course before Academy III. As a tip, many attend III as an experienced engineer but in hind sight wish they attended II first for a more rounded foundation to work from.